Recent upsizing of integrated circuits have made it further difficult to carry out a test for detecting failures in manufactured circuits. In order to solve this problem, a scan design (test) technique is adopted for designing circuits. A logic circuit in an integrated circuit is basically made up of a sequential circuit and a combinational circuit. According to the scan design technique, inputs and outputs to/from all flip-flops constituting the sequential circuit are connected to the combinational circuit, and also serially connected to each other so as to constitute a scan path. In this state of things, a data pattern is set in each flop—flop, a clock is supplied thereto, data is supplied from the combinational circuit to the flip-flops, and consequently the sets of data are serially fetched out. In this manner, functions as a circuit are tested. This test is useful for examining various patterns. In this way, values of the respective flip-flops are set and observed through external inputs and outputs and a scan path, i.e. the flip-flops constituting the sequential circuit are seen as external input/output, so that the flip-flops constituting the sequential circuit are tested in the similar manner as a combinational circuit.
FIG. 3 is a block diagram showing circuitry of a logic circuit 1 adopting a typical scan design test technique. This logic circuit 1 is made mainly of a combinational logic circuit 2 and a scan-path circuit 3. In the scan-path circuit 3, all flip-flops f1–fn (hereinafter, n=4 in all figures) of the logic circuit 1 which is subjected to the test are included. In the logic circuit 1, the combinational logic circuit 2 is made up of all circuits other than the sequence elements such as the flip-flop f1–fn. For simplicity, external inputs and outputs connected to the combinational logic circuit 2 are omitted from the figure.
In normal operation, in response to a clock commonly supplied from the outside to input terminal ck, the respective flip-flops f1 through fn fetch signals through respective inputs a1 through an and output the signals through respective outputs b1–bn, in repeating fashion. As a result, an arithmetic process is carried out in the combinational logic circuit 2.
Meanwhile, when conducting the test above, an appropriate signal sequence is supplied to an input terminal d0, and the flip-flops f1 through fn are caused to function as shift registers. Through the outputs b1 through bn, the signal sequence is supplied to the combinational logic circuit 2, thereby causing the combinational logic circuit 2 to carry out an arithmetic process. Subsequently, the result of the arithmetic process is fetched through the inputs a1 through an, and the flip-flops f1 through fn are again caused to function as the shift registers. As a result, the test result is observed through the output terminal b0. Appearing on the input terminal c0 connected to the outside is a control signal for causing the flip-flops f1 through fn to operate as the shift registers.
Prior to this test of the combinational logic circuit 2, the signal appearing on the input terminal c0 causes the flip-flops f1–fn to operate as the shift registers. In this state, if a scan input is supplied from the input terminal d0 to a first-stage output d1, the scan input is serially shifted from the outputs b1 through bn−1 to the inputs d1 through dn−1 in the next stage. Consequently, the presence of a failure on the scan path is identified by checking whether or not the scan input is serially outputted to the outside through the last-stage output bn and the output terminal b0.
In this manner, before being used for testing the combinational logic circuit 2, the flip-flops f1 through fn are subjected to the test. If the test confirms that these flip-flops f1 through fn function properly, the test of the combinational logic circuit 2 is carried out.
However, the above-described technique has such a problem that, although the presence of a failure on the scan path can be identified according to the scan output from the output terminal b0, the location of the failure cannot be identified. For instance, one cannot distinguish a 1-stuck-at fault of the output b3 of the flip-flop f3 from a 1-stuck-at fault of the output b2 of the flip-flop f2, because the scan output on the output terminal is a logical “1” in both cases.
If there is a test for not only identifying the presence of a failure but also specifying the location of the failure, such a test can be utilized for analyzing the failure. More specifically, with such a test, the analysis of the failure is promptly carried out in view of the specified location, and the result of the analysis is swiftly fed back to the design and process, so that the yield and reliability of chips are significantly improved.
Representative examples of failure models are the above-mentioned 1-stuck-at fault which causes a signal line to be stuck (fixed) at high and 0-stuck-at fault which causes a signal line to be stuck (fixed) at low. In many cases, failure models other than these stuck-at faults can be interpreted by the stuck-at fault. The stuck-at fault is thus the most common failure model for logic circuits.
Japanese Laid-Open Patent Application No. 2-10178/1990 (Tokukaihei 2-10178; published on Jan. 12, 1990) is an example of a conventional art for specifying the location of a failure. FIG. 4 is a block diagram showing circuitry of a logic circuit 11 corresponding to this conventional art. Being similar to the above-described logic circuit 1, the logic circuit 11 includes a combinational logic circuit 2 and a scan-path circuit 3. In addition to these members, however, the logic circuit 11 further includes a parity circuit 12. Note that, members having the same functions as those in the logic circuit 1 are given the same numbers, so that the descriptions are omitted for the sake of convenience.
The parity circuit 12 is made up of cascaded XOR gates 1 through gn−1 which perform XOR operation on the respective outputs b1 through bn of the flip-flops f1 through fn constituting the scan path. The location of a failure on the scan path is specified by the timing of the change of a parity output go on the last-stage XOR gate n−1.
FIG. 5 illustrates how a 1-stuck-at fault of the output b3 of the flip-flop f3 is detected. First, a test pattern including only a logical “0” is supplied to the input terminal d0. The shift register does not properly operate with this test pattern, so that, in a cycle 4, a logical “1” appears on the output terminal b0. Next, to the input terminal d0, a test pattern in which a first pattern is a logical “1” and second and subsequent patterns are logical “0” is supplied. Referring to the number of clocks from the supply of the first pattern to the reversal of the logic state, the location of the defected flip-flop f3 is specified.
In FIG. 5, it is determined that high-level is a logical “1” and low-level is a logical “0”. In shaded areas, the logic state is indeterminate. As the figure shows, when n=4, clock cycles 0–4 correspond to a test for checking the presence of a failure on the scan path, while cycles 5–9 correspond to a test for specifying the location of the failure. Since the flip-flop f3 is at fault, an abnormal logic state is detected in the cycle 8.
Such a conventional art makes it possible to specify the location of a failure but requires a lot of test cycles for realizing it. That is to say, when n=4, while the presence of a failure is checked with 5 cycles, at least 9 cycles are required for specifying the location of the failure. In this manner, a period of time required by the latter test is substantially twice as much as a period of time required by the former test. This period of time for specifying the location of the failure lengthens as the number of stages in one scan path increases.